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dc.contributor.authorBeyer, Dirk
dc.contributor.authorJakobs, Marie-Christine
dc.contributor.authorLemberger, Thomas
dc.contributor.authorWehrheim, Heike
dc.contributor.editorBecker, Steffen
dc.contributor.editorBogicevic, Ivan
dc.contributor.editorHerzwurm, Georg
dc.contributor.editorWagner, Stefan
dc.date.accessioned2019-03-14T11:49:21Z
dc.date.available2019-03-14T11:49:21Z
dc.date.issued2019
dc.identifier.isbn978-3-88579-686-2
dc.identifier.issn1617-5468
dc.identifier.urihttp://dl.gi.de/handle/20.500.12116/20907
dc.description.abstractSoftware verification received lots of attention in the past two decades. Nonetheless, it remains an extremely difficult problem. Some verification tasks cannot be solved automatically by any of today’s verifiers. To still verify such tasks, one can combine the strengths of different verifiers. A promising approach to create combinations is conditional model checking (CMC). In CMC, the first verifier outputs a condition that describes the parts of the program state space that it successfully verified, and the next verifier uses that condition to steer its exploration towards the unverified state space. Despite the benefits of CMC, only few verifiers can handle conditions. To overcome this problem, we propose an automatic plug-and-play extension for verifiers. Instead of modifying verifiers, we suggest to add a preprocessor: the reducer. The reducer takes the condition and the original program and computes a residual program that encodes the unverified state space in program code. We developed one such reducer and use it to integrate existing verifiers and test-case generators into the CMC process. Our experiments show that we can solve many additional verification tasks with this reducer-based construction.en
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofSoftware Engineering and Software Management 2019
dc.relation.ispartofseriesLecture Notes in Informatics (LNI) - Proceedings, Volume P-292
dc.subjectConditional Model Checking
dc.subjectTesting
dc.subjectSoftware Verification
dc.subjectSequential Combination
dc.titleCombining Verifiers in Conditional Model Checking via Reducersen
dc.typeText/Conference Paper
dc.pubPlaceBonn
mci.reference.pages151-152
mci.conference.sessiontitleSession 14: Programmanalyse und Verifikation II
mci.conference.locationStuttgart, Germany
mci.conference.date18.-22. Februar 2019
dc.identifier.doi10.18420/se2019-46


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